Thermal performance of logic chip in a package-on-package structure

ABSTRACT

Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention generally relate to integratedcircuit chip packaging and, more specifically, to a package-on-package(POP) packaging system with a high power chip and a low power chip.

2. Description of the Related Art

With the development of the electronics industry, there are increasingdemands for smaller electronic devices with improved performance. Inorder to achieve a higher integration density and a smaller footprint ofelectronic components, a so-called “package-on-package (POP)” technologyhas been developed. POP is a three-dimensional packaging technology usedto vertically stack a plurality of leadframe-based semiconductorpackages atop each other with an interface to route signals betweenthem.

Minimizing the thickness of the package has been a challenge to thesuccessful implementation of the POP technology since there is generallya trade-off between the thermal management of chips and other devicescontained in the package and the performance of the devices.Specifically, by locating memory chips, passive devices, and otherlow-power components of an IC package as close as possible to thecentral processor unit (CPU) and other high-power devices in an ICpackage, communication between devices in the IC package is acceleratedand packaging parasitics are reduced. However, heat generated byhigher-power chips is known to adversely affect memory chips and otherdevices positioned nearby. Consequently, it is not thermally feasible tostack memory chips and passive devices directly on or under a CPU orother high-power chip when incorporated into a single IC package, sincesuch a configuration necessarily limits the power of the high-power chipor affects the performance of the memory chips.

As the foregoing illustrates, there is a need in the art for a packagesystem having a greater density of integrated circuits with acorresponding reduction in package size. More particularly, there is aneed for a high-power chip and a low-power chip arrangement in avertical stack which prevents heat transfer between the chips.

SUMMARY OF THE INVENTION

Embodiments of the present invention set forth an IC system in which oneor more low-power chips can be positioned proximate high-power chipswithout suffering the effects of overheating. In one embodiment, the ICsystem includes a high-power chip mounted on a first packagingsubstrate, and a low-power chip disposed on a second packaging substratewhich is positioned above the first packaging substrate to form a stack.A thermal conductive pad is attached to a bottom surface of the firstpackaging substrate, and is in thermal communication with a portion of aprinted circuit board positioned below the first packaging substrate. Aplurality of thermal conductive features are formed through the firstpackaging substrate to thermally connect the high-power chip and theheat conductive pad.

One advantage of the present invention is that a memory chip or otherlow-power chip can be positioned in close proximity to a high-power chipthat is mounted on a packaging substrate in the same IC system withoutbeing overheated by the high-power chip. By having thermal conductivefeatures formed through the first packaging substrate to thermallyconnect the high-power chip and a thermal conductive pad that ispositioned between (and in thermal communication with) the firstpackaging substrate and the printed circuit board, heat generated by thehigh-power chip can be effectively dissipated into the printed circuitboard, which serves as a heat sink for the IC system. In this manner,the lifetime of the low-power chip is extended.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 is a schematic cross-sectional view of an integrated circuit (IC)system, according to one embodiment of the invention.

FIG. 2 is a schematic bottom view of a first packaging substrate showingan exemplary arrangement of a thermal conductive pad with respect tosolder balls.

For clarity, identical reference numbers have been used, whereapplicable, to designate identical elements that are common betweenfigures. It is contemplated that features of one embodiment may beincorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

FIG. 1 is a schematic cross-sectional view of an integrated circuit (IC)system 100, according to one embodiment of the invention. The IC system100 generally includes multiple IC chips and/or other discretemicroelectronic components, and is configured to electrically andmechanically connect said chips and components to a printed circuitboard 190. The IC system may be a vertical combination, i.e., a stackedconfiguration, of one or more high-power chips 101 and one or morelow-power chips 102. In this disclosure, the high-power chip 101 may bea high-power processor, such as a central processing unit (CPU), agraphics processing unit (GPU), application processor or other logicdevice, or any IC chip capable of generating enough heat duringoperation to adversely affect the performance of low-power chip 101 orpassive devices located in the IC system 100. For example, a high-powerchip is typically one that generates at least 10 W of heat or moreduring normal operation. Conversely, a low-power chip is one that doesnot generate enough heat during operation to adversely affect theperformance of adjacent IC chips or devices. For example, a low-powerchip is any IC chip that generates on the order of about 1 W of heat,i.e., no more than about 5 W, during normal operation. Low-power chipsmay be passive devices located in the IC system 100, for example amemory device, such as RAM or flash memory, an I/O chip, or any otherchip that does not generate over 5 W in normal operation.

In the embodiment shown in FIG. 1, the IC system 100 includes ahigh-power chip 101 disposed on a top surface 143 of a first packagingsubstrate 110 and a pack of low-power chips 102 disposed on a topsurface 106 of a second packaging substrate 140. The first packagingsubstrate 110 is substantially parallel to and opposing the secondpackaging substrate 140, with the high-power chip 101 sandwiched betweenthe first packaging substrate 110 and the second packaging substrate140. The second packaging substrate 140 is disposed over a top surface143 of the first packaging substrate 110 and is electrically connectedto the first packaging substrate 110 through electrical connections 142.The electrical connections 142 between the second packaging substrate140 and the first packaging substrate 110 may be made using anytechnically feasible approach known in the art, such as a solder bump ora solder ball. The electrical connections 142 may be in physical contactwith corresponding bond pads 145 formed on the top surface 143 of thefirst packaging substrate 110. It is contemplated that the electricalcommunication between the second packaging substrate 140 and the firstpackaging substrate 110 may also be made by other bonding techniques,such as a flip-chip bonding technique or a pin grid array (PGA)technique.

The low-power chip 102 mounted on the second packaging substrate 140 maybe encapsulated in a molding material 148 to protect the chip 102. Thehigh-power chip 101 is in electrical communication with the firstpackaging substrate 110 through electrical connections 104, such asmicrobumps. If desired, reliability of electrical connections 104 may beimproved by protecting the electrical connections 104 with anencapsulant material 108. The molding or encapsulant material may be aresin, such as epoxy resin, acrylic resin, silicone resin, polyurethaneresin, polyamide resin, polyimide resin, etc. Any other technicallyfeasible packaging techniques may be used to protect the low-power chip102 or electrical connections 104 of the high-power chip 101 to thefirst packaging substrate 110. While not shown, it is contemplated thatthe top side 150 of the molding material 148 facing away from the secondpackaging substrate 140 may be attached to a heat sink or other coolingmechanism to enhance the thermal transmittance of the IC system 100.

The low-power chip 102 is mounted opposite the high-power chip 101 in astacked configuration, and is electrically connected to the high-powerchip 101 and the PCB 190 via conductive traces 114 and conductive vias123 formed in the first packaging substrate 110. The electricalconnection between the high-power chip 101 and the first packagingsubstrate 110 may be made using any technically feasible approach knownin the art. It is noted that conductive traces 114 and conductive vias123, and configuration thereof, are exemplary approaches that can beused to electrically connect the high-power chip 101 to externalcomponents. Any known electrical connection with a different routingarrangement/configuration may be used in lieu of or in addition to theuse of conductive traces 114 and conductive vias 123.

In the embodiment illustrated in FIG. 1, a thermal conductive pad 160 isattached to a bottom surface 147 of the first packaging substrate 110.The thermal conductive pad 160 and the thermal conductive features 125to be discussed below are configured to facilitate heat flow from thehigh-power chip 101 to the PCB 190. The thermal conductive pad 160 maybe secured to the first packaging substrate 110 through an adhesivelayer 162. The adhesive layer 162 may be a metal-adhesive layercomprising at least one of TiN, Cu, Ni, Ag, Ti, Ta, W, TiN, WN, TiW, orany suitable material such as thermally-conductive epoxy resin. Thethermal conductive pad 160 may be made of a metal such as copper,aluminum, gold, silver, iron, alloys of two or more elements, polymer,or stainless steel. In one example, the thermal conductive pad 160 ismade of copper.

The thermal conductive pad 160 may be disposed at the central region onthe bottom surface 147 of the first packaging substrate 110. Thelocation of the thermal conductive pad 160 may be adjusted in accordancewith the thermal conductive features 125. The thermal conductive pad 160may occupy a surface area about 10% to about 100% of the first packagingsubstrate 110. In one example, the thermal conductive pad 160 coversabout 20% to about 60% surface area of the first packaging substrate110. It may be advantageous in certain embodiments to make the thermalconductive pad 160 electrically conductive so that it can serve as anelectrical connection between the first packaging substrate 110 and thePCB 190. In other words, the thermal conductive pad 160 can replace someof the solder balls 180 mounted to the bottom surface 147 of the firstpackaging substrate 110 that are used for electrically connecting thefirst packaging substrate 110 to the PCB 190.

FIG. 2 is a schematic bottom view of the first packaging substrate 110showing an exemplary arrangement of the thermal conductive pad 160 withrespect to the solder balls 180. It is contemplated that the thermalconductive pad 160 may vary in size depending upon the need for heatdissipation and/or electrical connection of the IC system 100.

The first packaging substrate 110 may include one or more thermalconductive features 125 embedded or formed therein for the purpose ofheat transfer. The thermal conductive features 125 are configured toconduct heat generated by the high-power chip 101 towards the PCB 190,which serves as a heat sink for the IC system 100. The thermalconductive features 125 may be parallel to each other at any desiredinterval. In the embodiment of FIG. 1 as shown, the thermal conductivefeatures 125 are vias running vertically through the first packagingsubstrate 110. It is contemplated that the thermal conductive features125 may be any known structure in the art and may be in any suitablearrangement, as long as the heat generated by the high-power chip 101can be effectively transmitted through the first packaging substrate 110to the thermal conductive pad 160 that is attached to the PCB 190. Incases where the thermal conductive features 125 are vias, they may beformed by laser drilling and filled with a thermal media such as copper.Any other suitable technique may be used to form thermal conductivefeatures 125. The thermal conductive features 125 may be formed andarranged in a way not interfering with the electrical traces 114 orconductive vias 123, or any other features in the first packagingsubstrate 110. While four thermal conductive features 125 are shown, itis understood that any number of the thermal conductive features 125 maybe used.

In various embodiments, the thermal conductive features 125 may have aheight “H₁” of about 200 μm to about 600 μm, for example about 400 μm.The thermal conductive pad 160 and the adhesive layer 162 may have aheight “H₂” of about 50 μm to about 250 μm, for example about 150 μm.

The thermal conductive features 125 thermally connect the high-powerchip 101 and the thermal conductive pad 160. Therefore, heat generatedby the high-power chip 101 is dissipated down through the firstpackaging substrate 110 to the thermal conductive pad 160 and then tothe PCB 190, rather than adversely affecting the low-power chip 102 thatis positioned above the high-power chip 101. If desired, some or all ofthe thermal conductive features may be made electrically conductive sothat they can be used to provide power and/or ground signals directlyfrom the PCB to the high-power chip 101. In such a case, the thermalconductive features may comprise copper, aluminum, gold, silver, oralloys of two or more electrical conductive elements.

It is contemplated that embodiments of the invention may be devisedwithout departing from the basic scope thereof. For example, instead ofmounting the high-power chip 101 on the top surface 143 of the firstpackaging substrate 110, the high-power chip 101 may be embedded withinthe first packaging substrate 110, with the thermal conductive features125 and the thermal conductive pad 160 configured in a similar way asdiscussed above to facilitate heat flow to the PCB 190.

The first packaging substrate 110 provides the IC system 100 withstructural rigidity and an electrical interface for routing input andoutput signals as well as power between the high-power chip 101, thelow-power chip 102, and the PCB 190. While not shown, it is contemplatedthat the first packaging substrate 110 may be a laminate substratecomprised of a stack of insulative layers. The conductive traces 114 andthe conductive vias 123, as discussed above, may be formed between theinsulative layers to provide electrical communication between thehigh-power chip 101, the low-power chip 102, and the PCB 190.

Suitable materials that may be used to make the first packagingsubstrate 110 and the second packaging substrate 140 include, but arenot limited to FR-2 and FR-4, which are traditional epoxy-basedlaminates, and resin-based Bismaleimide-Triazine (BT) from MitsubishiGas and Chemical. FR-2 is a synthetic resin bonded paper having athermal conductivity in the range of about 0.2 W/(K-m). FR-4 is a wovenfiberglass cloth with an epoxy resin binder that has a thermalconductivity in the range of about 0.35 W/(K-m). BT/epoxy laminatepackaging substrates also have a thermal conductivity in the range ofabout 0.35 W/(K-m). Other suitably rigid, electrically isolating, andthermally insulating materials that have a thermal conductivity of lessthan about 0.5 W/(K-m) may also be used.

In sum, embodiments of the invention set forth an IC system in which oneor more low-power chips are vertically positioned above one or morehigh-power chips mounted on a packaging substrate proximate thelow-power chips in the same IC system without suffering the effects ofoverheating. By having thermal conductive features formed through thepackaging substrate and thermally connected to a thermal conductive padattached to the bottom surface of the packaging substrate, the heatgenerated by the high-power chips can be effectively dissipated into aPCB, which is in thermal communication with the thermal conductive padand serves as a heat sink for the IC system. Therefore, heat transferfrom the high-power chips to the low-power chips is prevented orminimized. As a result, the lifetime of the memory chip is extended.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

We claim:
 1. A integrated circuit system, comprising: a first substrate;a high-power chip disposed on a first side of the first substrate; athermal conductive pad disposed on a second side of the first substrate,the second side being parallel to and opposing the first side; one ormore thermal conductive features formed in the first substrate, whereinthe one or more thermal conductive features thermally connect thehigh-power chip and the thermal conductive pad; and a heat sink attachedto a surface of the thermal conductive pad, wherein the heat sink is inthermal communication with the thermal conductive pad.
 2. The system ofclaim 1, further comprising: a low-power chip disposed on a secondsubstrate, wherein the second substrate is positioned adjacent the firstside of the first substrate.
 3. The system of claim 2, wherein thesecond substrate is positioned above the first substrate.
 4. The systemof claim 2, wherein the heat sink is a printed circuit board.
 5. Thesystem of claim 3, wherein the low-power chip, the high-power chip, andthe printed circuit board are in electrical communication with eachother.
 6. The system of claim 1, wherein the thermal conductive pad ispositioned at a central region of the first substrate.
 7. The system ofclaim 1, wherein the thermal conductive pad occupies a surface areaabout 10% to about 100% of the first substrate.
 8. The system of claim7, wherein the thermal conductive pad occupies the surface area about20% to about 60% of the first substrate.
 9. The system of claim 1,wherein the thermal conductive pad is electrically conductive.
 10. Thesystem of claim 1, wherein the thermal conductive pad comprises copper,aluminum, gold, silver, iron, alloys of two or more elements, polymer,or stainless steel.
 11. The system of claim 10, wherein the thermalconductive pad comprises copper.
 12. The system of claim 1, wherein theone or more thermal conductive features are vias running verticallythrough the first substrate.
 13. The system of claim 1, wherein the oneor more thermal conductive features are electrically conductive.
 14. Thesystem of claim 2, wherein the high-power chip generate at least 10 W ofheat during normal operation and the low-power chip generate less than 5W of heat during normal operation.
 15. A integrated circuit system,comprising: a first substrate, the first substrate having a first sideand a second side parallel and to the first side; a high-power chipembedded within the first substrate; a thermal conductive pad disposedon the second side of the first substrate; one or more thermalconductive features formed in the first substrate, wherein the one ormore thermal conductive features thermally connect the high-power chipand the thermal conductive pad; and a heat sink attached to a surface ofthe thermal conductive pad, wherein the heat sink is in thermalcommunication with the thermal conductive pad.
 16. The system of claim15, further comprising: a low-power chip disposed on a second substrate,wherein the second substrate is positioned relatively above the firstside of the first substrate and is in electrical communication with thefirst substrate.
 17. The system of claim 16, wherein the high-power chipgenerate at least 10 W of heat during normal operation and the low-powerchip generate less than 5 W of heat during normal operation.
 18. Thesystem of claim 15, wherein the thermal conductive pad is electricallyconductive.
 19. The system of claim 15, wherein the one or more thermalconductive features are vias running vertically through the firstsubstrate.
 20. The system of claim 15, wherein the heat sink is aprinted circuit board and is in electrical communication with thethermal conductive pad.